As the demand for better computer calculation performance increases, and particularly in regard to extension of floating point unit of next generation by Binary IEEE format which requires the support of JAVA programs, additional Logic is required in the Add-normalization path. The performance timing is most critical for the floating point units and prior art techniques could only achieve an addition of two floating point numbers mostly in three consecutive calculation steps
(1)--adding the mantissas, PA0 (2)--counting the leading zero digits, PA0 (3)--subtract the number of leading zero digits from the exponent to get the normalized exponent result. This work is usually a serialized work, i.e. a subsequent step can be calculated only when the preceding step is completed.
Some improvements to avoid the serialization time delay were presented in U.S. Pat. No. 5,392,228. Here, the normalizer employs a combination of LZA (leading zero anticipation) and LZD (leding zero detection) techniques. The LZA employed has an accuracy of +/- one bit position and thus can nearly determine the position of the leading one before the add result of the mantissas addition is available. Once the main add result is available, a mask is provided from the LZA output which is ANDed with the Add result to provide an accurate determination of the leading one position. This result is passed to both the shifting multiplexers and the exponent adjustment logic to compute the final floating point result. This so called `big LZD` arrangement, however, requires a significantly larger area to implement compared to a strictly serialized implementation.
Despite this additional area consumption which could be tolerated in many applications the previously mentioned normalizer needs a further calculation step to convert the leading zero count into a normalized exponent result.
Further, it does not provide an exact result of the leading zero count and an additional mask operation step is necessary after the main add result is present to obtain the exact leading zero count, thus an additional time delay is required to perform this calculation step.
With the present extension to 128-bit mantissas the time consuming effect of a strictly serialized work would be aggravated, and the previously described normalizer would consume even more area and a larger calculation time.
In view of the above discussion, it should be apparent to those persons of ordinary skill in the art that a need exists for a method and system which saves calculation time.